Multi-thread graphics processing system

ABSTRACT

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.17/661,824, filed May 3, 2022, which is a continuation of U.S.application Ser. No. 17/167,717, filed on Feb. 4, 2021, which is acontinuation of U.S. application Ser. No. 16/424,145, filed on May 28,2019 (now U.S. Pat. No. 10,957,007), which is a continuation of U.S.application Ser. No. 15/901,603 (now U.S. Pat. No. 10,346,945), filedFeb. 21, 2018, which is a continuation of U.S. application Ser. No.15/006,802 (now U.S. Pat. No. 9,922,395), filed Jan. 26, 2016, which isa continuation of U.S. application Ser. No. 14/299,600 (now U.S. Pat.No. 9,904,970), filed Jun. 9, 2014, which is a continuation of U.S.application Ser. No. 13/846,210 (now U.S. Pat. No. 8,749,563), filedMar. 18, 2013, which is a continuation of U.S. application Ser. No.11/746,446 (now U.S. Pat. No. 8,400,459), filed May 9, 2007, which is acontinuation of U.S. application Ser. No. 10/673,761 (now U.S. Pat. No.7,239,322), filed Sep. 29, 2003, all of which are incorporated herein bythis reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates generally to graphics processing and morespecifically to the interleaving of ALU operations with texture fetchingoperations.

Background Art

In a graphics processing system, it is important to manage and controlmultiple command threads relating to texture applications. In a typicalgraphics processing system, the processing elements, such as verticesand/or pixels, are processed through multiple steps providing for theapplication of textures and other processing instructions, such as donethrough one or more arithmetic logic units (ALU). To improve theoperating efficiency of a graphics processing system, the control of theflow of the multiple command threads is preferred.

FIG. 1 illustrates a prior art sequencing system 100. The system 100includes a first arbiter 101, a second arbiter 102 and a third arbiter103 and multiple buffers 104, 106, 108 and 110. In a typical embodiment,the buffers are first in and first out (FIFO) buffers. Each of thebuffers 104-110 include multiple command threads, such as 112, 114, 116,118 stored therein. Moreover, the system 100 is divided into resourcedivisions, such as an ALU resource division 120 and a texture fetchresource division 122. In the ALU resource division 120, the commandthread 118 may be received from an input command 124 as selected by thearbiter 101. The command thread 118 may then be withdrawn from thereservation stations 104 and 108 for the purpose of being provided to anALU (not shown) and the command threads within the texture fetchresource division 122 maybe withdrawn from the reservation stations 106and 110 to be provided to a texture fetch processors (not shown).

In the prior art embodiments of FIG. 1 , the first buffer 104 receivesan input command 124 and outputs a completed command thread 126 to thesecond arbiter 102. In one embodiment, the command thread may include anindicator, such as a flag, indicating when the access to the ALUresources has been completed for the associated command. The arbiter 102receives the input command 124 and thereupon provides, in due course,the command thread to either an appropriate texture fetch buffer 110 oran ALU buffer 108. Thereupon, the steps are repeated where an outputthread command 128 is provided to another ALU (not shown) or texturefetch processor (not shown) and returned to the buffer 108 or 110. Thebuffer 110 also produces the output 132 which is a command thread. Theoutput 132 may be provided to another arbiter 103 to be provided furtheralong the graphics processing pipeline.

The embodiment of FIG. 1 illustrates an inflexible system havingspecifically delineated ALU resource buffers and texture fetch resourcebuffers such that command threads must be sequentially provided betweenthe various buffers 104, 106, 108 and 110. Furthermore, the system 100of FIG. 1 does not support an unlimited number of dependent fetchesbased on the structure of the buffer 104-110 structure and connectivitybetween each other and with respect to available ALU resources andtexture fetch resources.

As such, there is a need for a sequencing system for providing for theprocessing of multi-command threads that supports an unlimited number ofdependent texture fetches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrate the schematic block diagram of a prior art commandthread processing system;

FIG. 2 illustrates a schematic block diagram of a multi-threadprocessing system, in accordance with one embodiment of the presentinvention;

FIG. 3 illustrates a schematic block diagram of a pipeline vectormachine in accordance with one embodiment of the present invention;

FIG. 4 illustrates a schematic block diagram of a multi-thread commandprocessing system in accordance with one embodiment of the presentinvention;

FIG. 5 illustrates a schematic block diagram of a graphics processingpipeline, in accordance with embodiment to the present invention;

FIG. 6 illustrates a flowchart of a method for multi-thread commandprocessing in accordance with one embodiment of the present invention;and

FIG. 7 illustrates a flowchart of an alternative method for multi-threadprocessing.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Generally, the present invention includes a multi-thread graphicsprocessing system and method thereof including a reservation stationhaving a plurality of command threads stored therein. A reservationstation may be any type of memory device capable of reserving andstoring command threads. Furthermore, a command thread is a sequence ofcommands applicable to the corresponding element, such as pixel commandthread relative to processing of pixel elements and a vertex commandthread relative to vertex processing commands. The system and methodfurther includes an arbiter operably coupled to the reservation stationsuch that the arbiter retrieves a first command thread of the pluralityof command threads stored therein. The arbiter may be any implementationof hardware, software or combination thereof such that the arbiterreceives the command thread and thereupon provides the command thread toa command processing engine. The system and method further includes thecommand processing engine coupled to receive the first command threadfrom the arbiter such that the command processor may perform at leastone processing command from the command thread. Whereupon, a commandprocessing engine provides the first command thread back to theassociated reservation station.

The command processing engine may be any suitable engine as recognizedby one having ordinary skill in the art for processing commands, such asa texture engine, an arithmetic logic unit, or any other suitableprocessing engine.

More specifically, FIG. 2 illustrates one embodiment of a multi-threadprocessing system 200 in accordance with one embodiment of the presentinvention. The system 200 includes a reservation station 202, an arbiter204 and a command processing engine 206. The reservation stationincludes a plurality of command threads 208, 210 and 212 forillustration purposes. In one embodiment, the command threads 208-212are graphic command threads as illustrated in FIG. 2 . As noted above,in one embodiment the reservation station 202 operates similar to afirst in first out (FIFO) memory device, although command threads208-212 may be retrieved from any location, whereas completed commandsexit the memory device in a FIFO manner. The arbiter 204 retrieves acommand thread via connection 214 and provides the retrieved commandthread to the command processing engine 206, such as a graphicsprocessing engine via connection 216. Thereupon, the command processingengine 206 performs a threaded command and provides a status update 218to the reservation station 202, more specifically to the correspondingcommand thread, such as 208, 210 or 212.

The present invention provides for the processing of multiple threads. Acommand thread may go idle while waiting for available processingresources, such as specific data to be retrieved. As such, multiplethreads prevent the corresponding resource from going idle. Furtherincluded within the command threads, 208-212, in one embodiment is anindicator, a done flag, which indicates when all of the commands withinthe command thread have been executed. Therefore, when all of thecommands in the command thread have been executed and the command threadis retrievable from the reservation station 202, the command thread maybe provided to a further processing element (not illustrated) within agraphics processing pipeline.

In one embodiment, the arbiter 204 retrieves the command threads 208-212based on a priority scheme. For example, the priority may be based onspecific commands that have been executed within a command thread orspecific commands which are to be executed within a command for theeffective utilization of the arbiter 204 and the command processingengine 206. In an alternative embodiment, the arbiter 204 may alwaysretrieve the oldest available thread.

In accordance with one embodiment to the present invention, FIG. 3illustrates a pipeline vector machine 230 including a multiple ALUsystem 232, a buffer 234 and sequencer logic 236, which may be an ALUresource. In one embodiment, the sequencer logic 236 receives a firstthread 242, and a second thread 244 from the buffer 234, such that thelogic 236 may perform simultaneous, interleaved execution of the commandthreads. Furthermore, the sequencer logic 236 is coupled to pipeline240. In one embodiment, pipeline 240 may be an eight stage deep pipelinefor providing vector analysis.

ALU arbitration proceeds in the same way as fetch arbitration. The ALUarbitration logic chooses one of the pending ALU clauses to be executed.The arbiter selects the command thread by looking at the reservationstations, herein vertex and pixel reservation stations, and picking thefirst command thread ready to execute. In one embodiment, there are twoALU arbiters, one for the even clocks and one for the odd clocks. Forexample, a sequence of two interleaved ALU clauses may resemble thefollowing sequence: (E and O stands for Even and Odd sets of 4 clocks)Einst0 Oinst0 Einst1 Oinst1 Einst2 Oinst2 Einst0 Oinst3 Einst1 Oinst4Einst2 Oinst0. As such, this way hides the latency of 8 clocks of theALUs. Moreover, the interleaving also occurs across clause boundaries,as discussed in greater detail below.

FIG. 4 illustrates another embodiment of a multi-thread commandprocessing system 300 having a first reservation station 302, a secondreservation station 304, an arbiter 306, an ALU 308 and a graphicsprocessing engine 310. In this embodiment, the first reservation station302 is a pixel reservation station such that the command threads 312,314 and 316 contain pixel-based commands therein. Furthermore, in thisembodiment the second reservation station 304 is a vertex reservationstation is directed towards vertex command threads illustrated ascommand threads 318, 320 and 322.

Although not illustrated in FIG. 4 , in one embodiment an input arbiterprovides the command threads to each of the first reservation station302 and the second reservation station 304 based on whether the commandthread is a pixel command thread, such as thread 312, or a vertexcommand thread, such as thread 318. In this embodiment, the arbiter 306selectively retrieves either a pixel command thread, such as commandthread 316, or a vertex command thread, such as command thread 322.

In one embodiment, each station 302, 304 maintains the state of eachthread, such as threads 312-322. In one embodiment, the thread lives ina given location in the station 302, 304, in the order that the threadis received therein. From each buffer, the arbiter 306, which may beimplemented as arbitration logic executed on a processing device,selects one thread for the graphics processing engine 310 and one threadfor the ALU 308. Once a thread is selected by the arbiter 306, thethread is marked as invalid and submitted to the appropriate executionunit 308 or 310. Upon the execution of the associated command of thecommand thread, the thread is thereupon returned to the station 302 or304 at the same storage location with its status updated, once allpossible sequential instructions have been executed.

With respect to FIG. 4 , a pixel command thread 324 may be retrieved bythe arbiter 306 and a vertex command thread 326 may also be retrieved.The arbiter 306 then provides one thread 328, which may be either 324 or326 to the graphics processing engine 310, such as a texture engine, andprovides the other thread 330 to the ALU 308.

Upon execution of the command, the ALU 308 then returns the commandthread 332 to the appropriate reservation station 302 or 304. Asillustrated in FIG. 4 , the ALU 308 is coupled to both reservationstation 302 and reservation station 304 for providing the thread backthereto. The same data transfer occurs when the graphic processingengine 310 performs the commands and returns the command thread 334 backto the originating reservation station 302 or 304. It is also noted,that in the present embodiment, multiple command operations may beperformed by a particular unit 308 or engine 310, but in order to switcha command thread from ALU 308 to a graphics processing engine 310, thatcommand thread must be returned back to the appropriate reservationstation 302 or 304 and re-retrieved by the arbiter 306 and thereuponprovided to the other unit 308 or engine 310 respectively.

In one embodiment, each command thread within the reservation station302 and 304 may be stored across two physical pieces of memory, whereina majority of bits are stored in a one read port device. The bitsrequired for the thread arbitration may be stored in a highlymulti-ported structure, such that the bit stored in the one read portdevice are termed state bits and the bits stored in the multi-read portdevice are termed status bits.

In one embodiment the state bit includes, but not limited to, a controlflow instruction pointer, a loop iterator, a call return pointer,predicated bits, a GPR base pointer, a context pointer, valid bits, andany other suitable bits as recognized by one having skill in the art. Itis also noted that in one embodiment, index pointers are not included inthe state bits, wherein one embodiment may be stored in the generalprocessing registers.

In this embodiment, the fields of the state bits, the control flowinstruction pointer, the execution count marker, loop iterators, callreturn pointers, predicate bits, are updated every time the thread isreturned to the reservation station 302 or 304 based on how muchprogress has been made on the thread execution. It is also noted that inthis embodiment, the GPR base pointer and context pointers are unchangedthroughout the execution of the thread.

In one embodiment, the status bits include: a valid thread bit, atexture/ALU engine needed bit, a texture reads are outstanding bit and awaiting on texture read to complete bit. In this embodiment, all of theabove status bit fields from the command threads go to the arbitrationcircuitry. Thereupon, the arbiter 306 selects the proper allocation ofwhich command thread goes to the graphics processing engine 310 andwhich command thread goes to the ALU 308. In this embodiment, two setsof arbitration are performed: one for pixels, such as command thread 316and one for vertices, such as command thread 322. Texture arbitrationrequires no allocation or ordering as it is purely based on selectingthe oldest thread that requires the graphics processing engine 310.

FIG. 5 illustrates a block diagram representing the further execution ofthe command threads upon completion of all embedded commands therein.The ALU 308 is coupled to a render backend 350 via connection 352 and toa scan converter 356 via connection 354. As recognized by one havingordinary skill in the art, the ALU 308 may be operably coupled to therender backend 350 such that the bus 352 incorporates one or more of aplurality of connections for providing the completed command thread,such as command thread 316 of FIG. 4 , thereto. Furthermore, asrecognized by one having ordinary skill in the art, ALU 308 may beoperably coupled to the scan converter 356 such that the connection 354may be one or more of a plurality of connections for providing theexecuted command thread, such as command thread 322 of FIG. 4 , to thescan converter 356. As discussed above, once the command thread'sindicator bit, such as the done flag, is set, indicating all of thecommands in the thread have been executed, the completed command threadis further provided in the processing pipeline. Moreover, the renderbackend 350 may be any suitable rendering backend for graphicsprocessing as recognized by one having ordinary skill in the art. Thescan converter 356 may be any suitable scan converter for graphicsprocessing as recognized by one having ordinary skill in the art.

FIG. 6 illustrates a flow chart for a method of multi-thread commandprocessing in accordance with one embodiment of the present invention.The method begins, step 400, by retrieving a selected command threadfrom a plurality of first command threads and a plurality of secondcommand threads, step 402. For example, as discussed above with regardto FIG. 4 , the selected command thread may be retrieved by the arbiter306. The next step, step 404, is providing the selected command threadto a graphics command processing engine. As discussed above regardingFIG. 4 , the arbiter 306 provides the selected command thread to thegraphics processing engine 310, which, in one embodiment may be atexture engine. In another embodiment, the arbiter 306 may provide theselected command thread to the ALU 308.

The method further includes performing a command in response to theselected command thread, step 406. In this embodiment the command isperformed by the graphics processing engine 310, which may be performinga texture operation. The next step, step 408, is writing the selectedcommand thread to a first reservation station if the selected commandthread is one of the plurality of first command threads and writing theselected command thread to a second reservation station if the selectedcommand thread is one of the plurality of second command threads. Withregard to FIG. 4 , if the selected command thread is a pixel commandthread, such as command thread 312-316, the graphics processing engine310 provides the command thread 312-316 back thereto via connection 332.Furthermore, if the command thread is from the vertex reservationstation 304, the command thread 318-320 may be provided thereto viaconnection 334 from the graphics processing engine 310. Thereupon, themethod is complete, step 410.

FIG. 7 illustrates a flowchart of an alternative method for multi-threadprocessing.

The method begins, step 420, by retrieving a selected command threadfrom a plurality of command threads, step 422, similar to step 402 ofFIG. 6 . The next step, step 424, is providing the selected commandthread to a graphics processing engine, similar to step 404 of FIG. 6 .

Thereupon, the method further includes performing a command in responseto the selected command thread, step 426, similar to step 406 of FIG. 6. The next step, step 428, is retrieving a second selected commandthread from the plurality of command threads. Similar to step 422, thesecond selected command thread may be retrieved from either a firstreservation station, such as reservation station 302 of FIG. 4 or asecond reservation station, such as reservation station 304 of FIG. 4 .

The method further includes providing the second command thread to thegraphics processing engine, step 430. The next step, step 432, is priorto writing the selected command thread to either the first reservationstation or the second reservation station, interleaving the selectedcommand thread and the second selected command thread. Thereupon, themethod further includes performing a second command in response to thesecond selected command thread, step 434.

In the embodiment where the graphics processing engine is a textureengine, the commands performed are directed to texture operations.Although, as recognized by one having ordinary skill in the art, anyother suitable graphics processing engine may be utilized.

The next step, step 436, is writing the second selected command threadto a first reservation station if the selected command thread is one ofa plurality of first command threads and writing the second selectedcommand thread to a second reservation station if the second selectedcommand thread is one of a plurality of second command threads.Furthermore, the method includes writing the selected command thread tothe first reservation station if the selected command thread is one ofthe plurality of first command threads and the selected command threadto the second reservation station if the selected command thread is oneof the plurality of second command threads, step 438. Once again, usingthe exemplary embodiment of FIG. 4 , the command threads, such as312-316 and/or 318-322 may be provided from the graphics processingengine 310 and written back thereto or in another embodiment may beprovided to the ALU 308 by the arbiter 306 and, upon execution of anarithmetic command, provided back to the associated reservation station,302 or 304 respectively.

As such, the present invention allows for multi-thread commandprocessing effectively using designated reservation station, inconjunction with the arbiter, for the improved processing of multiplecommand threads. The present invention further provides for theeffective utilization of the ALU and the graphics processing engine,such as the texture engine, for performing operations for both pixelcommand threads and vertex command threads, thereby improving graphicsrendering and improving command thread processing flexibility.

It should be understood that there exists implementations of othervariations and modifications of the invention and its various aspects,as may be readily apparent to those of ordinary skill in the art, andthat the invention is not limited by the specific embodiments describedherein. For example, the storage capacity of the reservation stationsmay be adequately adjusted to accommodate the storage any suitablecorresponding number of command threads. It is therefore contemplatedand covered by the present invention any and all modifications,variations, or equivalents that fall within the scope of the basicunderlying principles disclosed and claimed herein.

1. A graphics processing system comprising: a sequencer logic configuredto: receive a first command thread and a second command thread from abuffer, wherein the first command thread and the second command threadrelate to application of textures; perform interleaved execution of thefirst command thread and the second command thread; and a pipeline,coupled to the sequencer logic, configured to provide vector analysis onthe executed first command thread and the second command thread.
 2. Thegraphics processing system of claim 1, wherein the sequencer logic is anmultiple arithmetic logic unit (ALU) system resource.
 3. The graphicsprocessing system of claim 1, wherein the pipeline is an eight stagedeep pipeline.
 4. The graphics processing system of claim 1, wherein thesequencer logic is further configured to select the first command threador the second command thread by: analyzing a vertex reservation stationand a pixel reservation station on which either the first command threador the second command thread are stored; and determining which of thefirst command thread or the second command thread is ready to execute.5. The graphics processing system of claim 4, wherein performing theinterleaved execution of the first command thread and the second commandthread is based on even and odd clock cycles.
 6. The graphics processingsystem of claim 5, wherein the sequencer logic is further configured toreturn the executed first command thread or the second command thread tothe vertex reservation station or the pixel reservation station fromwhich it originated.
 7. The graphics processing system of claim 1,wherein the first command thread or the second command thread are storedacross two physical pieces of memory.
 8. The graphics processing systemof claim 7, wherein a majority of bits of the first command thread orthe second command thread are stored in a one read port device.
 9. Thegraphics processing system of claim 7, wherein bits of the first commandthread or the second command thread required for thread arbitration arestored in a multi-ported structure.
 10. The graphics processing systemof claim 7, wherein the two physical pieces of memory are physicallyseparated.
 11. A method of operating a graphics processing systemcomprising: receiving, by a sequencer logic, a first command thread anda second command thread from a buffer, wherein the first command threadand the second command thread relate to application of textures;performing, by the sequencer logic, interleaved execution of the firstcommand thread and the second command thread; and providing, by apipeline coupled to the sequencer logic, vector analysis on the executedfirst command thread and the second command thread.
 12. The method ofclaim 11, wherein the sequencer logic is an multiple arithmetic logicunit (ALU) system resource.
 13. The method of claim 11, wherein thepipeline is an eight stage deep pipeline.
 14. The method of claim 11,further comprising selecting, by the sequencer logic, the first commandthread or the second command thread by: analyzing a vertex reservationstation and a pixel reservation station on which either the firstcommand thread or the second command thread are stored; and determiningwhich of the first command thread or the second command thread is readyto execute.
 15. The method of claim 14, wherein performing theinterleaved execution of the first command thread and the second commandthread is based on even and odd clock cycles.
 16. The method of claim15, further comprising returning, by the sequencer logic, the executedfirst command thread or the second command thread to the vertexreservation station or the pixel reservation station from which itoriginated.
 17. The method of claim 11, wherein the first command threador the second command thread are stored across two physical pieces ofmemory.
 18. The method of claim 17, wherein a majority of bits of thefirst command thread or the second command thread are stored in a oneread port device.
 19. The method of claim 17, wherein bits of the firstcommand thread or the second command thread required for threadarbitration are stored in a multi-ported structure.
 20. The method ofclaim 17, wherein the two physical pieces of memory are physicallyseparated.